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AMBA APB Peripherals Cores




The AMBA APB Peripherals Cores are a family of AMBA APB Bus peripherals cores that provide system functions for SOCs. System functions provided by these cores include interrupt control, reset control, timers and counters, General Purpose I/Os (GPIOs), and Serial Peripheral Interface (SPI). These cores connect seamlessly to the AMBA APB Bus. The AMBA APB Peripherals Cores are available as synthesizable Verilog models from Aurora VLSI, Inc. Contact CustomerService@auroravlsi.com.

Interrupt Controller

  • 32 interrupt requests- independently enabled, level or edge sensitive, active high or low
  • 8 interrupt outputs (configurable)
  • Each interrupt request is assigned to one or more interrupt outputs that it will trigger
  • 32 interrupt request priority levels
  • Priority level of highest priority interrupt request for each interrupt output is available for vectored interrupt handling
  • Software interrupt set and clear

Timers and Counters

  • Up to eight 32 bit timers and/or counters
  • Independently enabled
  • Configurable to count always (timer) or count events (counter)
  • Events can be level or edge sensitive, active high or active low
  • Increment or decrement (configurable)
  • Reload and continue counting, or stop upon expiration (configurable)
  • Timers/counters can be chained for 64 bit timers/counters
  • Supports clock scaling for timer function, external clock for timer function, watchdog interrupt and reset signaling, and other typical timer/counter functions

General Purpose I/Os (GPIOs)

  • 32 GPIOS
  • Register or bypass mode selected independently for each GPIO
  • Independent direction control for each GPIO
  • Independent interrupt enable for each GPIO

Serial Peripheral Interface (SPI)

  • Master mode including multi master capability, and slave mode
  • Transmit and receive SPI word lengths up to 32 bits- software configurable
  • MSB or LSB transferred first- software configurable
  • Implements all SPI clock polarity and clock phase modes
  • DMA support
  • Independently maskable interrupts- SPI word transfer complete, FIFO empty and full, FIFO underrun and overrun, master collision

Reset Controller

  • Up to 32 reset outputs (configurable)- asserted high or low (configurable)
  • Configurable reset de-assertion delay up to 64K cycles for each reset output
  • 2 pin reset requests- nonmaskable, asynchronously asserted, synchronously de-asserted, asserted high or low (configurable)
  • 2 interrupt/watchdog reset requests- individually maskable for each reset output, synchronously asserted, synchronously de-asserted, asserted high or low (configurable)
  • Software reset requests- individually asserted by software for each reset output, synchronously asserted, synchronously de-asserted


AMBA APB Peripherals Cores


Interrupt Controller + AMBA APB Bus interface


Timers + AMBA APB Bus interface


General Purpose I/Os (GPIOs) + AMBA APB Bus interface


Serial Peripheral Interface (SPI) + AMBA APB Bus interface


Reset Controller + AMBA APB Bus interface


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