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The Ethernet MAC Cores are a family of Ethernet Media Access Controller Cores that provide an Ethernet peripheral for SOCs. Both Ethernet 10/100 and 10/100/1000 Cores are available. Within the Ethernet MAC Core family, there are cores with generic application side interfaces and cores with AMBA AHB Bus interfaces. The cores with AMBA AHB Bus interfaces connect seamlessly to the AMBA AHB Bus and include a DMA Engine to move the Ethernet frame data. These Ethernet MAC Cores are available as synthesizable Verilog models from Aurora VLSI, Inc. Contact CustomerService@auroravlsi.com.
Ethernet MAC
- 10Mb/s, 100Mb/s, or 1Gb/s Ethernet line speeds
- Industry standard interfaces to the PHY- RMII, MII, RGMII, GMII, TBI
- Full and half duplex
- Automatic retries after collision, programmable retry counter
- Automatic padding and removal of PAD bytes to meet minimum frame size
- FCS generation for transmitted packets, and checking on received packets
- MDIO interface for PHY management
- Programmable address filtering
- Frame status captured in 2 Status FIFOs
- Transmit Data FIFO (configurable size)
- Receive Data FIFO (configurable size)
DMA/AMBA Interface
- AMBA AHB Bus interface
- 2 channel DMA Engine- transmit and receive DMA channels
- Physical DMA addresses
- Programmable DMA starting address
- Programmable DMA transfer count- up to 64 Kbytes
- Programmable DMA AMBA Bus interface transaction size- 8 to 1024 bytes
- Programmable DMA AMBA Bus data transfer size- 4 or 8 bytes
- Locked DMA operation optional (software programmable)
- Direct software writes or information extracted from descriptors in memory, to program DMA control information
- Dedicated AMBA Bus master interface for each DMA channel
- AMBA Bus slave interface for register reads and writes
- Interrupts- transmit/receive frame DMA completed, frame transmit/receive completed
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