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The PCI Bus Interface Cores are a family of PCI Bus and CardBus Interface Cores that provide master and slave PCI Bus and CardBus functionality for SOCs. Both 32 bit and 64 bit PCI Buses, and CardBus are supported. These cores are compatible with both 33MHz and 66MHz PCI Buses. Within the PCI Bus Interface Core family, there are cores with generic application side interfaces and cores with AMBA AHB Bus interfaces- PCI/AMBA AHB bridges. The PCI/AMBA AHB bridges connect seamlessly to the AMBA AHB Bus and include a DMA Engine to move the data. These PCI Bus Interface Cores are available as synthesizable Verilog models from Aurora VLSI, Inc. Contact CustomerService@auroravlsi.com.
PCI Bus Interface
- PCI 2.1 and 2.2 compliant
- Functionality- 32 bit or 64 bit address and data transfers
- Supports variable burst size transfers
- Performs zero wait state transfers
- Master performs I/O, Memory, and Configuration types of PCI transfers
- Master supports byte mode operation
- Master performs Memory Write Invalidate and Memory Read Line operations
- Performs back to back transfers
- PCI master transaction status captured in 4 entry PCI Master Status FIFO
CardBus
- All 32 bit PCI functionality
- Plus CardBus compliant
- Includes CardBus STSCHG signal
- CardBus power management states D0, D1, D2, and D3 supported
DMA/AMBA Interface
- AMBA AHB Bus interface
- Single channel DMA Engine for PCI master memory and I/O transactions
- Physical DMA addresses
- Programmable DMA starting address
- Programmable DMA transfer count- up to 64 Kbytes
- Programmable DMA AMBA Bus interface transaction size- 8 to 1024 bytes
- Programmable DMA AMBA Bus data transfer size- 4 or 8 bytes
- Locked DMA operation optional (software programmable)
- Direct software writes or information extracted from descriptors in memory, to program DMA control information
- Dedicated AMBA Bus master interface for the DMA channel
- Dedicated AMBA Bus master interface for PCI slave transactions
- AMBA Bus slave interface- register accesses, PCI master configuration transactions
- Interrupts- PCI master read and write data DMA completed, PCI master transaction status available, software interrupt, PCI bus reset, PCI Bus interrupt, and CardBus interrupts
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