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SDRAM Controller Cores

 

 

 

The SDRAM Controller Cores are a family of SDRAM Controller Cores that provide an SDRAM interface peripheral for SOCs. Memory Controller combination cores that include SDRAM, SRAM, and Flash Cores are also available. Within the SDRAM Controller Core family, there are cores with generic application side interfaces and cores with AMBA AHB Bus interfaces. The cores with AMBA AHB Bus interfaces connect seamlessly to the AMBA AHB Bus as AMBA AHB Bus slaves. These SDRAM Controller Cores are available as synthesizable Verilog models from Aurora VLSI, Inc. Contact CustomerService@auroravlsi.com.

SDRAM Controller

  • 32 bit or 64 bit memory interface data bus
  • 4 Mbyte to 4 Gbyte SDRAM memory systems
  • 1, 2, or 4 external SDRAM banks
  • Programmable number of address bits
  • Pipelined accesses for highest possible performance
  • Fully programmable SDRAM parameters- CAS latency, number of internal banks, refresh interval, timing parameters, etc.

AMBA Slave Interface

  • AMBA AHB Bus slave
  • 32 bit or 64 bit AMBA AHB Bus- user configurable
  • Supports all required AMBA AHB Bus features
  • Implements AMBA Bus timeout and RETRY response
  • Read data prefetching
  • Write data packing
  • Same cycle device request/response is supported for highest throughput
  • Handles all data packing/unpacking and data alignment for data transfer sizes that do not match the AMBA Bus width and/or SDRAM data bus width
  • User configurable for big or little endian AMBA Bus and memory
  • AMBA Bus and SDRAM interfaces can be asynchronous to each other

 

SDRAM Controller Cores

AU-M2000

SDRAM controller

AU-MB2000

SDRAM controller + AMBA AHB interface

AU-MB2001

3 port SDRAM controller + AMBA AHB interface

 

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