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The USB 2.0 Device Cores are a family of USB 2.0 Device Controller Cores that provide a USB 2.0 device peripheral for SOCs. Both a low gate count four endpoint core and a ten endpoint core are available. Within the USB 2.0 Device Core family, there are cores with generic application side interfaces and cores with AMBA AHB Bus interfaces. The cores with AMBA AHB Bus interfaces connect seamlessly to the AMBA AHB Bus and include a DMA Engine to move the USB transaction data. These USB 2.0 Device Cores are available as synthesizable Verilog models from Aurora VLSI, Inc. Contact CustomerService@auroravlsi.com.
USB 2.0 Device
- Up to ten endpoints
- EP0- control endpoint, accepts SETUP, IN, and OUT control transactions
- EP1- interrupt endpoint, accepts IN and OUT interrupt transactions
- EP2, EP4, EP6, EP8- IN endpoints; accept IN bulk and isochronous transactions
- EP3, EP5, EP7, EP9- OUT endpoints; accept OUT bulk and isochronous transactions
- 8 or 16 bit UTMI interface
DMA/AMBA Interface
- AMBA AHB Bus interface
- 2 channel DMA Engine
- IN DMA channel- bulk/iso IN data from each bulk, iso, and interrupt IN endpoint to the USB 2.0 Device block
- OUT DMA channel- bulk/iso OUT data from the USB 2.0 Device block to each bulk, iso, and interrupt OUT endpoint
- Physical DMA addresses
- Programmable DMA starting address
- Programmable DMA transfer count- up to 64 Kbytes
- Programmable DMA AMBA Bus interface transaction size- 8 to 1024 bytes
- Programmable DMA AMBA Bus data transfer size- 4 or 8 bytes
- Locked DMA operation optional (software programmable)
- Direct software writes or information extracted from descriptors in memory, to program DMA control information
- 2 AMBA Bus master interfaces- one for IN data, one for OUT data
- AMBA Bus slave interface for register reads and writes
- Interrupts- DMA completed, IN transaction data sent, OUT transaction data received
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