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The USB OnTheGo (OTG) Cores are a family of USB 2.0 combined device controller and host controller cores that provide a USB 2.0 OnTheGo (OTG) peripheral for SOCs. Both USB OTG Type A and Type B Cores are available. The USB OTG Cores include the required control and interrupt device endpoints, plus eight bulk/iso transfer device endpoints. When in host mode, the DMA Engine supports the Universal Host Controller Interface (UHCI) and Extended Host Controller Interface (EHCI). Within the USB OTG Core family, there are cores with generic application side interfaces and cores with AMBA AHB Bus interfaces. The cores with AMBA AHB Bus interfaces connect seamlessly to the AMBA AHB Bus and include a DMA Engine to move the USB transaction data. These USB OTG Cores are available as synthesizable Verilog models from Aurora VLSI, Inc. Contact CustomerService@auroravlsi.com.
USB 2.0 OTG
- Dual mode USB 2.0 controller- USB 2.0 device controller and USB 2.0 host controller
- USB high speed and full speed operation
- Session Request Protocol (SRP) supported in both device and host modes
- Host Negotiation Protocol (HNP) supported in both device and host modes
- 4 or 8 bit ULPI (low pin count UTMI+) interface
USB 2.0 Device
- Ten endpoints- EP0 (control endpoint), EP1 (interrupt endpoint), four IN endpoints, and four OUT endpoints
- Includes device control pipe registers and USB Descriptor RAMs at EP0
- USB device command execution in EP0
USB 2.0 Host Controller
- Initiates all required USB high speed and full speed transaction types
- One downstream port
- UHCI (full speed operation) and EHCI (high speed operation) support
- UHCI and EHCI list and transaction descriptor processing in conjunction with DMA
DMA/AMBA Interface
- AMBA AHB Bus interface
- 2 channel DMA Engine
- Physical DMA addresses
- Programmable DMA starting address
- Programmable DMA transfer count- up to 64 Kbytes
- Programmable DMA AMBA Bus interface transaction size- 8 to 1024 bytes
- Programmable DMA AMBA Bus data transfer size- 4 or 8 bytes
- Locked DMA operation optional (software programmable)
- Direct software writes or information extracted from descriptors in memory, to program DMA control information
- 3 AMBA Bus master interfaces- DMA transmit data, DMA receive data, non-DMA
- AMBA Bus slave interface for register reads and writes
- Interrupts- device mode and host mode
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