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The Utopia Cores provide a Utopia 1/2/2+/3/3+ peripheral subsystem for SOCs. They contain a Utopia 1/2/2+/3/3+ Interface between UTOPIA/POS-PHY compliant PHY Chips and the application layers such as ATM. Within the Utopia Core family, there are cores with generic application side interfaces and cores with AMBA AHB Bus interfaces. The cores with AMBA AHB Bus interfaces connect seamlessly to the AMBA AHB Bus and include a DMA Engine to move the packet/cell data. These Utopia Cores are available as synthesizable Verilog models from Aurora VLSI, Inc. Contact CustomerService@auroravlsi.com.
Utopia 1/2/2+/3/3+
- Supports both ATM Forum’s standards and Saturn Group’s POS-PHY Interface standards.
- Programmable option for U1, U2, U2+(or POS-PHY Level 2), U3, and U3+ standards.
- Supports both packet and cell level transfers.
- Number of ports for polling can be programmed.
- Receive Ports can be enabled or disabled dynamically.
- Transfer (PHY/core transfer length for every transfer) count can be independently programmed for each port with a maximum of 64 bytes.
- Round robin mechanism of polling on the receive side.
- Parity generation/checking with a programmable polarity option.
- User defined (through Verilog parameters) FIFO sizes for all transmit and receive FIFOs.
- Supports synchronous memories for FIFOs.
- Synthesis options for receive only, transmit only, or both receive and transmit.
DMA/AMBA Interface
- AMBA AHB Bus interface
- 2 channel DMA Engine- transmit and receive DMA channels
- Physical DMA addresses
- Programmable DMA starting address
- Programmable DMA transfer count- up to 64 Kbytes
- Programmable DMA AMBA Bus interface transaction size- 8 to 1024 bytes
- Programmable DMA AMBA Bus data transfer size- 4 or 8 bytes
- Locked DMA operation optional (software programmable)
- Direct software writes or information extracted from descriptors in memory, to program DMA control information
- Dedicated AMBA Bus master interface for each DMA channel
- AMBA Bus slave interface for register reads and writes, Transmit Address FIFO writes, Transmit Status FIFO reads
- Interrupts- transmit/receive DMA completed, FIFO empty/full thresholds
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